Materials Considerations for Next-Gen Semiconductor Architectures, Part 1 of 2

July 07,2015

The semiconductor industry has been going through some rapid and radical metamorphoses over the past few years, as it decides the best route to address consumer-driven needs for more of most things: more data; more memory bandwidth; more performance; and lower power. Moore’s law is reaching its limits. Mobile and wireless computing, as well as the Internet of Things (IoT), calls for taking other elements into consideration, such as battery size and life, security and integration of MEMS, sensors and RF devices. What does this mean for the consumable suppliers to the semiconductor industry? In this two-part interview, Dow’s Ethan Simon, Cheng Bai Xu, Jeff Calvert, George Lu, and Robin Fahey collaborated to present the opportunities and challenges this poses for Dow Electronic Materials.

In Part 1 of this series, we look at how the transition from 2D to 3D architectures, from 3D transistors, to 3D packaging and 3D-IC processes, as well as the transition to 450-mm diameter wafers is affecting advanced semiconductor materials development.

Questions:
The industry will enter a new 14-nm 3D FinFET generation in 2015 and semiconductor manufacturing processes and technology are encountering unprecedented challenges, such as the transition from 2D devices relying on lithography to 3D devices relying on the coordinated development of multiple technologies. We need plenty of innovation in device structure, new materials and processes, which is very challenging. Could you share your views on semiconductor scaling, rising costs and increasing process complexity?

What makes our current industry situation interesting from the perspective of consumable suppliers is the nearly equal importance of (a) new technologies for new nodes with (b) the customization of existing technologies for the continually growing segments of “lower-tech devices.”

We need new technologies because semiconductor processes are becoming more complex and are requiring tighter control over device dimensions. For example, advanced nodes require much more precise control over film thickness, over a wide range of length scale. Here are a few examples. Current mainstream logic processes require wafer-scale thickness variation of <20 nm for each film layer in the front end. This requirement will become tighter in subsequent nodes. 3D FinFET device processes have planarization requirements of 10 nm and gap fill requirements of 5 nm. These are really small dimensions! For reference, the diameter of a strand of human DNA is 2.5 nm.

At the same time, there is increased use of existing design rules for 3D memory architectures and for the billions of “low-tech” devices needed to fuel the growth of the IoT and the increasing use of micromechanical devices in cell phones, cars, and medical devices. Examples of the devices, often called MEMS devices, are accelerometers, gyroscopes, pressure sensors, and flowmeters.

As a consumable supplier we must work both sides of the equation. We have to help our customers solve leading edge, challenging technical problems, and we have to continue to make older technologies more cost-effective.

The semiconductor industry continues to explore new technologies, such as 3D-IC and TSV, FinFET, EUV, 450mm wafer and others. What do you think the trends will be in terms of applications and development activities in 2015? What are the opportunities and challenges for the semiconductor industry in 2015?

We need new technologies because semiconductor processes are becoming more complex and are requiring tighter control over device dimensions. For example, advanced nodes require much more precise control over film thickness, over a wide range of length scale. Here are a few examples. Current mainstream logic processes require wafer-scale thickness variation of <20 nm for each film layer in the front end. This requirement will become tighter in subsequent nodes. 3D FinFET device processes have planarization requirements of 10 nm and gap fill requirements of 5 nm. These are really small dimensions! For reference, the diameter of a strand of human DNA is 2.5 nm.

At the same time, there is increased use of existing design rules for 3D memory architectures and for the billions of “low-tech” devices needed to fuel the growth of the IoT and the increasing use of micromechanical devices in cell phones, cars, and medical devices. Examples of the devices, often called MEMS devices, are accelerometers, gyroscopes, pressure sensors, and flowmeters.

As a consumable supplier we must work both sides of the equation. We have to help our customers solve leading edge, challenging technical problems, and we have to continue to make older technologies more cost-effective.

The semiconductor industry continues to explore new technologies, such as 3D-IC and TSV, FinFET, EUV, 450mm wafer and others. What do you think the trends will be in terms of applications and development activities in 2015? What are the opportunities and challenges for the semiconductor industry in 2015?

FinFET is established, 3D is growing and TSV is beginning to grow. Fabs have established process of record processes for these areas and will continue to work with suppliers to optimize consumable sets for the next nodes. For example, there is need for improvements to large-area planarization and bulk material removal rates in some 3D processes. CoO for TSV processes continue to be important. EUV and 450mm technologies are further out. 193i multiple patterning is the technology of choice for 10nm, and new products to enabling cost-effective 193i multiple patterning will be a focus in 2015. Most consumable suppliers are already ready for 450-mm wafer technologies, so this will not be a focus in 2015.

Device packaging technologies will also continue to scale to increasingly fine-pitch and novel design layouts (such as fan-out wafer-level packaging (FOWLP)) to support greater I/O counts, while also seeing more development and early-stage manufacturing in 3D stacked architectures. One of the primary challenges for 2.5D and 3D-IC stacking is thin wafer handling: wafers are typically thinned to 50 µm prior to subsequent processing steps. Handling is done by temporarily bonding them to a carrier wafer prior to backside processing, and the wafers are finally debonded following backside processing. Working with industry partners, Dow has made significant progress developing a temporary wafer bonding material based on our benzocyclobutene resin technology.

We continue to investigate new technologies including EUV and directed self-assembly for CD shrinking. Meanwhile, we are actively working on other advanced materials targeted at extending 193nm lithography and making for a more cost-effective 193nm multiple patterning process.

Conclusion
With all of these new developments and advanced processes, this is a challenging but exciting time to be a materials supplier to the semiconductor manufacturing market. In 
Part 2 of this interview , we take materials considerations to the next level, beyond device manufacturing and the challenges that come with the IoT and heterogeneous integration.

Update: See part 2 of this interview, released August 6, 2015,  Material Considerations for the IOT and Heterogeneous Integration .

FinFET is established, 3D is growing and TSV is beginning to grow. Fabs have established process of record processes for these areas and will continue to work with suppliers to optimize consumable sets for the next nodes. For example, there is need for improvements to large-area planarization and bulk material removal rates in some 3D processes. CoO for TSV processes continue to be important. EUV and 450mm technologies are further out. 193i multiple patterning is the technology of choice for 10nm, and new products to enabling cost-effective 193i multiple patterning will be a focus in 2015. Most consumable suppliers are already ready for 450-mm wafer technologies, so this will not be a focus in 2015.

Device packaging technologies will also continue to scale to increasingly fine-pitch and novel design layouts (such as fan-out wafer-level packaging (FOWLP)) to support greater I/O counts, while also seeing more development and early-stage manufacturing in 3D stacked architectures. One of the primary challenges for 2.5D and 3D-IC stacking is thin wafer handling: wafers are typically thinned to 50 µm prior to subsequent processing steps. Handling is done by temporarily bonding them to a carrier wafer prior to backside processing, and the wafers are finally debonded following backside processing. Working with industry partners, Dow has made significant progress developing a temporary wafer bonding material based on our benzocyclobutene resin technology.

We continue to investigate new technologies including EUV and directed self-assembly for CD shrinking. Meanwhile, we are actively working on other advanced materials targeted at extending 193nm lithography and making for a more cost-effective 193nm multiple patterning process.

Conclusion
With all of these new developments and advanced processes, this is a challenging but exciting time to be a materials supplier to the semiconductor manufacturing market. In 
Part 2 of this interview , we take materials considerations to the next level, beyond device manufacturing and the challenges that come with the IoT and heterogeneous integration.

Update: See part 2 of this interview, released August 6, 2015,  Material Considerations for the IOT and Heterogeneous Integration .