As packaging technologies endeavor to address the higher performance and increased functionality called for by today’s electronic devices, efforts to achieve the necessary I/O densities have brought traditional C4 bumps to their limits, and the industry is rapidly turning to Cu pillars as a solution for fine pitch bumping. Tin-silver caps have become the solder capping material of choice. In this interview, Dr. Jianwei Dong, Global Marketing Manager, Advanced Packaging Technologies, Dow Electronic Solutions, explains why.
Q: What are the main drivers for the adoption of tin-silver capped copper pillars in advanced semiconductor designs? Why not use tried-and-true solder bumping technology?
JD: The main reason for the switch from C4 bumps to Cu pillars is to enable much-finer-pitched bumps to accommodate more I/Os on a single chip. Die sizes are not getting larger; if anything, they are decreasing in size, which increases the challenge of how many I/Os can be put on the die. There is a physical limitation for C4 bump size because of cross talk due to bridging and shorts that occur during bump collapse. Cu pillars stand up to mass reflow and the thermocompression bonding processes, and therefore allow for finer pitch sizes without worrying about bridging and shorts, and can achieve finer geometries overall. However, while Cu-Cu direct bonding is ideal, processes are still in development due to technical challenges. So it is still necessary to rely on a tin-silver (SnAg) cap to bond two dies.
Q: How are copper pillars enabling 2.5D and 3D-IC packaging?
JD: The central element of 2.5D and 3D-IC packaging is 3D through silicon via (TSV). TSVs provide lines of passage of signal, thermal and power through the die, forming the interconnects to the interposer in the case of 2.5D, or another die, in the case of 3D-IC. However, TSVs don’t directly bond to each other. An additional interconnect structure is still required to connect chips and enable multilevel stacking. Pitch requirements of TSVs call for another level of Cu pillar—called “µpillar”—to allow for stacking at these tighter pitch requirements. Achieving this calls for a high-yielding µpillar plating and assembly process to enable 3D-IC assembly.
Q. What are the challenges with using solder materials, such as tin-silver, for capping copper pillars, and how can these challenges be overcome?
JD: Solder materials for capping processes have to address two application groups. One is the standard pillar that measures anywhere from 35-75µm diameter. Today’s standard Cu pillars are 50µm. The second application is µpillar, for which the diameter of the Cu pillar is significantly smaller in the 10-20µm range. While electroplated SnAg is being adopted as caps on µpillars, because of the size, the plating process becomes even more challenging in two ways: solder cap morphology control and silver composition control.
Morphology control affects the within-die thickness uniformity of solder structures, which directly impacts assembly yield. Silver composition is critical for ensuring long-term device reliability. A non-uniform distribution of Ag results in Ag3Sn intermetallic compound (IMC) growth that prematurely cracks the solder. The more silver in the solder structure, the more Ag3Sn IMCs there are. This is an issue for µpillars because the silver composition tends to be higher than C4 bumps and the uniformity control is more difficult.
Overcoming these challenges is more in the hands of chemistry design than in anything else. The SnAg plating chemistry has to address both the morphology and silver composition issues. Traditionally, the plating chemistry was designed for large C4 applications, where the two issues were not as prominent as they are today. Now, in µpillar applications, it’s critical to tune the chemistry to make sure there is a smooth morphology and well-controlled silver composition. It’s up to the formulation to enable this.
Q: What is the minimum size for capped Cu pillars?
JD: The minimum size is limited only by people’s imagination. The smallest size we’ve seen successfully and reliably demonstrated is 2.5µm, with µpillars smaller than 10µm diameter used in demo devices. To be sure, the electroplating process is not a limiting factor on super-small-size capped Cu pillars, and neither is the chemistry. The tools and materials exist. They may, however, be limited by assembly, test, design and cost.
Q: What is next for tin-silver capping? Are there any remaining challenges that still need to be addressed?
JD: In packaging, just because a new technology comes along doesn't mean the previous generation goes away. For SnAg chemistry, that means making sure it can be adapted to a wide range of applications from Cu capping to µpillars. It needs to be robust and flexible enough to accommodate all applications on the same tool platform. As 2.5D and 3D evolve to smaller-size pillars, our job is to make sure that when we accommodate the next-generation pillar, we don’t lose sight of mainstream C4 bumping processes.
Another challenge is to create a more user-friendly experience. Developing SnAg chemistry takes a lot of learning and investment. It involves putting several key additives into a bath and maintaining a long-term balanced and stable performance in a fab environment. To make sure the plating process delivers stable yield, bath metrology and proper replenishment are a must. At Dow Electronic Solutions, we are working with our plating and metrology tool partners to create a true turn-key solution for customers so they won’t have to worry about bath management, process adaptability, and yield loss. We make sure the yield is always high and the process is robust. As with any technology, there are always improvements needed to keep up with the pace of change. We will relentlessly innovate with our customers and partners to stay ahead of the curve on SnAg solder plating technology.