Dow’s Litho and CMP Teams to Present at CSTIC 2016

March 02,2016

The China Semiconductor Technology International Conference (CSTIC) will be held March 13-14, 2016 in conjunction with SEMICON China in Shanghai. The conference provides an international forum for academic researchers, industrial practitioners and engineers from around the world to share information on state-of-the-art research in all aspects of semiconductor technology and manufacturing, including devices, design, lithography, integration, materials, processes, and manufacturing, as well as emerging semiconductor technologies and silicon material applications.

The China Semiconductor Technology International Conference (CSTIC) will be held March 13-14, 2016 in conjunction with SEMICON China in Shanghai. The conference provides an international forum for academic researchers, industrial practitioners and engineers from around the world to share information on state-of-the-art research in all aspects of semiconductor technology and manufacturing, including devices, design, lithography, integration, materials, processes, and manufacturing, as well as emerging semiconductor technologies and silicon material applications.

Dow is proud to be a participant in this leading-edge forum, and will present papers about some of its recent work in lithography and chemical mechanical planarization (CMP) technology:

Sunday, March 13, 2:40-3:10 pm
Symposium V: CMP and Post-CMP Cleaning

Session I: Advanced CMP Applications: Pad and Slurry Technologies for sub 28nm CMP Process Challenges
Charles Lin, Dow Electronic Materials

This invited presentation provides an overview of how Dow CMP solutions address advanced process challenges. First, it will look at Dow’s pad and slurry consumables and their interaction with the CMP process performance response. Then, it will discuss key components in product design that influence overall CMP process performance. Additionally, it will emphasize Dow’s application engineering capabilities that provide comprehensive CMP manufacturing solutions for the semiconductor industry. Case studies will illustrate how Dow’s technology delivers exceptional CMP process performance.

Monday, March 14, 1:30-2:00 pm
Symposium II: Lithography and Patterning

Session V: Multiple Patterning: Moore or Less? The Map Grows Increasingly Complex as Materials and Processes Abound
Dr. Pete Trefonas, Dow Electronic Materials

This keynote presentation will detail the fundamental materials challenges underpinning successful lithography process performance, including topics such as managing shot noise and origins of stochastic effects, which impact resolution and line width roughness, as well as defectivity. New materials designs for photoresist will be described, including designer monomers, photoacid generators, quenchers, and polymer sequencing control, which are designed to tackle these challenges. The designs allow greater determinism in the location of polymer chains within the film. New materials that go above and below the film, as well as materials to modify the resist sidewalls post-processing, offer even more opportunities for pattern enhancement.

We hope you’ll join us at this year’s CSTIC conference to learn more about how Dow is enabling the next generation of semiconductor manufacturing with our CMP and lithography materials and applications engineering expertise.

Dow is proud to be a participant in this leading-edge forum, and will present papers about some of its recent work in lithography and chemical mechanical planarization (CMP) technology:

Sunday, March 13, 2:40-3:10 pm
Symposium V: CMP and Post-CMP Cleaning

Session I: Advanced CMP Applications: Pad and Slurry Technologies for sub 28nm CMP Process Challenges
Charles Lin, Dow Electronic Materials

This invited presentation provides an overview of how Dow CMP solutions address advanced process challenges. First, it will look at Dow’s pad and slurry consumables and their interaction with the CMP process performance response. Then, it will discuss key components in product design that influence overall CMP process performance. Additionally, it will emphasize Dow’s application engineering capabilities that provide comprehensive CMP manufacturing solutions for the semiconductor industry. Case studies will illustrate how Dow’s technology delivers exceptional CMP process performance.

Monday, March 14, 1:30-2:00 pm
Symposium II: Lithography and Patterning

Session V: Multiple Patterning: Moore or Less? The Map Grows Increasingly Complex as Materials and Processes Abound
Dr. Pete Trefonas, Dow Electronic Materials

This keynote presentation will detail the fundamental materials challenges underpinning successful lithography process performance, including topics such as managing shot noise and origins of stochastic effects, which impact resolution and line width roughness, as well as defectivity. New materials designs for photoresist will be described, including designer monomers, photoacid generators, quenchers, and polymer sequencing control, which are designed to tackle these challenges. The designs allow greater determinism in the location of polymer chains within the film. New materials that go above and below the film, as well as materials to modify the resist sidewalls post-processing, offer even more opportunities for pattern enhancement.

We hope you’ll join us at this year’s CSTIC conference to learn more about how Dow is enabling the next generation of semiconductor manufacturing with our CMP and lithography materials and applications engineering expertise.