ECTC 2018 Forges New Frontiers for Heterogeneous Integration

May 22,2018

With headliners like Big Data, artificial intelligence, human-to-machine interface, and other emerging applications enabled by heterogeneous integration, the 68th Electronics Components Technologies Conference (ECTC 2018) is the place to be for advanced electronics packaging devotees May 29-June 1, 2018. This year, San Diego gets its turn at hosting the event, and an anticipated 1400+ attendees are expected to turn up for the festivities.

The ECTC technical committee has packed a lot of content into four days. From an emerging technology session on soft material-enabled electronics for medical, health, and human-machine interfaces; to a panel discussion on IC/package co-design for heterogeneous integration; and a keynote talk on cost and supply chain implications of advanced packaging for artificial intelligence (AI), autonomous vehicles, and wearables; the opportunities for inspiration are unlimited.

Dow Electronic Materials is once again a Gold sponsor of ECTC and is honored to have its experts and technology featured in two technical presentations during the event. Mark your calendars and be on the lookout for the following presentations:

Co-integration of High-Bandwidth Photonics and High-Speed Electronics on 2.5D Glass Interposers Using Low Optical Absorption Photoimageable Dielectric Polymer
Session 24, Optical Module Integration
Thursday, May 31, 3:55 pm

Many of today’s emerging technologies targeting AI, augmented and virtual reality (AR/VR), autonomous vehicles, and internet of things (IoT) devices are backed by optical interconnect technologies to provide high connectivity and bandwidth. While optical interconnects have proven to be an effective solution for long-distance telecommunications, adapting them for chip-to-chip communications is proving to be a costly endeavor. Silicon photonic integration with CMOS is being investigated as a solution.

This presentation offers an approach for integrating single-mode waveguides for high-bandwidth photonics and fine-line redistribution layers RDL structure for high-speed electronics on 2.5D glass interposers using Dow’s benzocyclobutene (BCB) based, low-optical-absorption, photoimageable dielectric polymer. The paper will be presented by Rui Zhang, Georgia Tech. Michael Gallagher and Ed Anzures from Dow co-authored the paper.

Void-Free Copper Pillar Hybrid Wafer Bonding Using a BCB Based Polymer Adhesive and Chemical Mechanical Polishing
Session 32, Heterogeneous Integration 
Friday, June 1, 1:30 pm

3D through silicon via (3D TSV) combined with Cu pillar structures allow electronic manufacturers to reduce die-to-die distance while maintaining device reliability. This approach is well suited for devices targeting data- and power-hungry high-performance computing applications, such as AI and machine learning.

Cu-Cu bonding has been an ongoing process challenge for 3D TSV stacks. Hybrid bonding approaches that bond copper-polymer structures using a copper dual damascene integration scheme have been investigated, but the Cu overburden continues to be an issue despite chemical mechanical polishing (CMP) steps. In one approach, while copper slurries removed the copper overburden and copper areas were successfully bonded, gaps between polymeric adhesive layers were visible after bonding.

This presentation by Dow’s Michael Gallagher, highlights two approaches that have been developed to planarize both the copper pillar and polymeric adhesive, either together in a non-selective CMP process or separately in a two-step process. Gallagher’s presentation suggests that partial cure of the BCB dielectric will advance the material enough for it to be planarized, while still allowing for sufficient material flow to achieve void-free bonding during final bonding cure.

FOW/PLP Consortium Presentations
As a member of the Fan-out Wafer and Panel-Level Packaging (FOW/PLP) Consortium, Dow is actively collaborating with other industry players in developing processes and technologies for this growing packaging platform. In this upcoming ECTC conference, the following papers, co-authored by our Global Strategic Marketing Director, Rozalia Beica, and Global Marketing Manager, Marc Lin, and covering a variety of critical items for fan-out will be presented.

Chip-First Fan-Out Panel Level Packaging for Heterogeneous Integration
 Cheng-Ta Ko, Kai-Ming Yang, Chen-Hao Lin, and Yu-Hua Chen – Unimicron Technology Corp.; John Lau and Ming Li – ASM Pacific Technology; Marc Lin – The Dow Chemical Company
Session 8: Fan-Out Packaging-Applications and Architectures
Wednesday, May 30, 3:55 PM

Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging (FOWLP) with Large Chips and Multiple Re-Distributed Layers (RDLs)
John Lau, Ming Li, Margie Li, Nelson Fan, and Eric Kuah – ASM Pacific Technology; Iris Xu, Tony Chen, Zhang Li, and Kim Hwee Tan – JCAP; Rozalia Beica – The Dow Chemical Company
Session 13: Fan-out and Interposer Connections
Thursday, May 31, 8:50 AM

Reliability of Fan-Out WaferLevel Packaging (FOWLP) with Large Chips and Multiple Re-Distributed Layers (RDLs)
John Lau, Ming Li, Margie Li, and Nelson Fan – ASM Pacific Technology; Xiangyong Qing, Koh Sau Wee, and Xi Cao – Huawei Technologies; Mian Tao and Jeffery Lo – Hong Kong University of Science and Technology; Rozalia Beica – The Dow Chemical Company
Session 34: Fan-out Wafer Level Package Reliability 
Friday, June 1, 1:30 PM

Interactive Presentation:

Fan-Out Wafer-Level Package for Heterogeneous Integration
Ming Li, Margie Li, Nelson Fan, Eric Kuah, and Kai Wu – ASM; Iris Xu, Tong Chen, Zhang Li, and KH Tan – JCAP; Rozalia Beica – Dow Chemical Company
Session 40: Posters 4
Thursday, May 31, 2:00-4:00pm

Please visit us during ECTC at booth #212.