Dow Presentations Provide Gold, Silver, and Copper Solutions for IoT Devices at IMPACT-IIAC 2016

November 09,2016

Playing off the popularity of the Internet of Things and the development of technologies required to support wearable devices and smart home applications, the IMPACT-IIAC 2016 Joint Conference, which took place Oct. 26-28 in Taipei, Taiwan, was aptly themed, "IMPACT on the Next Big Things," and included panel sessions, invited talks, industrial sessions and paper presentations on topics related to accelerating manufacturing and commercialization of smart, connected devices.

Now in its 11th year, it was the first time organizers of IMPACT—which stands for International Microsystems, Packaging, Assembly and Circuits Technology Conference—joined forces with organizers of the iMAPS All Asia Conference (IIAC) to present the IMPACT-IIAC 2016 Joint Conference, in conjunction with TPCA Show 2016. The conference and show were organized by IEEE CPMT-Taipei, iMAPS-Taiwan, ITRI and TPCA. IIAC traditionally rotates around Asian semiconductor hubs, and in the past has joined forces with ICEP.

While members of academia presented most of the event papers, Dow Electronic Materials was honored to be among the industry experts chosen to present. Each of Dow’s four papers addressed different process challenges with innovative chemistries from its broad portfolio; focusing on gold, silver and copper technologies, respectively.

In "New Immersion Gold Technology for Uniform Au Thickness Distribution," presenter Jian Zhang talked about both the advantages and challenges of using electroless nickel immersion gold as a final finishing technique for printed circuit boards (PCBs). He also offered a new approach that addresses the challenges.

On the upside, Au’s low reactivity can protect PCB’s underlying Ni and Cu surfaces from oxidation to allow for longer storage. It provides excellent surface planarity suitable for soldering, especially for tiny parts such as BGA and flip chip; and the surface remains solderable even after multiple reflow cycles. It is useful for contact surfaces such as membrane switches and contact points, and may also be used for wire bonding.

On the down side, when used for final PCB finish, Au is susceptible to differences in surface potential—something known as the galvanic effect —and can result in nonuniform deposition that then leads to other issues. The most critical of these is Au skip-plating, or black Ni, because of Ni over-dissolution on specific pads, resulting in a solderability problem.

Dow’s new immersion gold technology can effectively reduce the galvanic effect by introducing a new chemical system that results in minimizing electropotential differences to provide a uniform gold deposition, and also allows for increased Au plating thickness. Download the full paper.

Also on the topic of immersion gold, Dow’s Willetta Lai presented "High performance Cyanide-free Immersion Gold," addressing the environmental hazards of using potassium gold cyanide as the gold source in the immersion gold bath. Potassium gold cyanide is known to be highly toxic to humans as well as the environment, particularly to aquatic life. Mishandling it or the gold bath may lead to release of cyanide gas. Unfortunately, there are few cyanide-free immersion gold bath chemistries available that demonstrate the bath stability, control and high-repeatability performance as those containing potassium gold cyanide.

Lai’s team at Dow has been working to solve this, and was pleased to present a novel cyanide-free immersion gold bath that can be applied in the ENIG process for continuous operation. Besides being free of cyanide, the bath characteristic can be operated at a lower temperature (45°C vs. 80°C) and has a neutral pH. This bath solves environmental concerns, as well as providing an energy-saving solution. Most importantly, the plating performance is equivalent to a conventional immersion gold bath. Download the full paper.

Dow’s Lok Lok Liu presented "A Potential Silver Catalyst System for New Generation of Electroless Cu Process as a Palladium Substitution," offering a cost-saving alternative to a critical step in electroless Cu plating onto insulating substrates like those used in PCB manufacturing: the surface activation of the dielectric surface for deposition in electroless copper bath.

Currently, this key step requires the use of a palladium catalyst. Because of the high and volatile unit metal price of palladium, the catalyst solution is the most expensive part of the electroless process. This is driving the industry to develop an alternative to palladium for the catalyst. Dow proposes using a silver catalyst, which shares similar characteristics to palladium in both ionic and metallic forms, because of the cost advantages as well as its excellent reliability performance.

In her presentation, Liu discussed the positive performance outcomes of using silver catalyst based on studies done on deposition profile, microvia coverage and morphology, and reliability with liquid-to-liquid thermal shock, providing the details of each. Download the full paper.

Lastly, "Next Generation Electrolytic Copper Plating Process for HDI Applications" was presented by Dow’s Nagarajan Jayaraju to address the challenging demands for micro-via filling for high-density interconnect (HDI) applications.

Copper electroplating is a critical step in fabricating the HDI substrates use as core layers in buildup applications. These substrates may contain vias and through holes with varying dimensions that make it challenging to meet via filling and hole throwing power (TP) requirements. As such, the industry is calling for thinner and uniform surface copper, void-free Cu electro-deposition in filled blind micro-vias (BMV) and higher throwing power (TP) in high aspect ratio through holes.

To meet these stringent requirements, Dow has developed a direct current plating process that provides via filling with higher TP in through holes while maintaining high plating rates and enabling high production.

Jayaraju’s presentation provided the details of the development process targeting micro-via fill of 60μm and 100μm deep vias, as well as the rigorous evaluation steps taken to make sure of its capability. He reported that this new process results in dimple depths of less than 10μm, and a void-free fill at a surface Cu thickness of less than 21 μm. Download the full paper.

Playing off the popularity of the Internet of Things and the development of technologies required to support wearable devices and smart home applications, the IMPACT-IIAC 2016 Joint Conference, which took place Oct. 26-28 in Taipei, Taiwan, was aptly themed, "IMPACT on the Next Big Things," and included panel sessions, invited talks, industrial sessions and paper presentations on topics related to accelerating manufacturing and commercialization of smart, connected devices.

Now in its 11th year, it was the first time organizers of IMPACT—which stands for International Microsystems, Packaging, Assembly and Circuits Technology Conference—joined forces with organizers of the iMAPS All Asia Conference (IIAC) to present the IMPACT-IIAC 2016 Joint Conference, in conjunction with TPCA Show 2016. The conference and show were organized by IEEE CPMT-Taipei, iMAPS-Taiwan, ITRI and TPCA. IIAC traditionally rotates around Asian semiconductor hubs, and in the past has joined forces with ICEP.

While members of academia presented most of the event papers, Dow Electronic Materials was honored to be among the industry experts chosen to present. Each of Dow’s four papers addressed different process challenges with innovative chemistries from its broad portfolio; focusing on gold, silver and copper technologies, respectively.

In "New Immersion Gold Technology for Uniform Au Thickness Distribution," presenter Jian Zhang talked about both the advantages and challenges of using electroless nickel immersion gold as a final finishing technique for printed circuit boards (PCBs). He also offered a new approach that addresses the challenges.

On the upside, Au’s low reactivity can protect PCB’s underlying Ni and Cu surfaces from oxidation to allow for longer storage. It provides excellent surface planarity suitable for soldering, especially for tiny parts such as BGA and flip chip; and the surface remains solderable even after multiple reflow cycles. It is useful for contact surfaces such as membrane switches and contact points, and may also be used for wire bonding.

On the down side, when used for final PCB finish, Au is susceptible to differences in surface potential—something known as the galvanic effect —and can result in nonuniform deposition that then leads to other issues. The most critical of these is Au skip-plating, or black Ni, because of Ni over-dissolution on specific pads, resulting in a solderability problem.

Dow’s new immersion gold technology can effectively reduce the galvanic effect by introducing a new chemical system that results in minimizing electropotential differences to provide a uniform gold deposition, and also allows for increased Au plating thickness. Download the full paper.

Also on the topic of immersion gold, Dow’s Willetta Lai presented "High performance Cyanide-free Immersion Gold," addressing the environmental hazards of using potassium gold cyanide as the gold source in the immersion gold bath. Potassium gold cyanide is known to be highly toxic to humans as well as the environment, particularly to aquatic life. Mishandling it or the gold bath may lead to release of cyanide gas. Unfortunately, there are few cyanide-free immersion gold bath chemistries available that demonstrate the bath stability, control and high-repeatability performance as those containing potassium gold cyanide.

Lai’s team at Dow has been working to solve this, and was pleased to present a novel cyanide-free immersion gold bath that can be applied in the ENIG process for continuous operation. Besides being free of cyanide, the bath characteristic can be operated at a lower temperature (45°C vs. 80°C) and has a neutral pH. This bath solves environmental concerns, as well as providing an energy-saving solution. Most importantly, the plating performance is equivalent to a conventional immersion gold bath. Download the full paper.

Dow’s Lok Lok Liu presented "A Potential Silver Catalyst System for New Generation of Electroless Cu Process as a Palladium Substitution," offering a cost-saving alternative to a critical step in electroless Cu plating onto insulating substrates like those used in PCB manufacturing: the surface activation of the dielectric surface for deposition in electroless copper bath.

Currently, this key step requires the use of a palladium catalyst. Because of the high and volatile unit metal price of palladium, the catalyst solution is the most expensive part of the electroless process. This is driving the industry to develop an alternative to palladium for the catalyst. Dow proposes using a silver catalyst, which shares similar characteristics to palladium in both ionic and metallic forms, because of the cost advantages as well as its excellent reliability performance.

In her presentation, Liu discussed the positive performance outcomes of using silver catalyst based on studies done on deposition profile, microvia coverage and morphology, and reliability with liquid-to-liquid thermal shock, providing the details of each. Download the full paper.

Lastly, "Next Generation Electrolytic Copper Plating Process for HDI Applications" was presented by Dow’s Nagarajan Jayaraju to address the challenging demands for micro-via filling for high-density interconnect (HDI) applications.

Copper electroplating is a critical step in fabricating the HDI substrates use as core layers in buildup applications. These substrates may contain vias and through holes with varying dimensions that make it challenging to meet via filling and hole throwing power (TP) requirements. As such, the industry is calling for thinner and uniform surface copper, void-free Cu electro-deposition in filled blind micro-vias (BMV) and higher throwing power (TP) in high aspect ratio through holes.

To meet these stringent requirements, Dow has developed a direct current plating process that provides via filling with higher TP in through holes while maintaining high plating rates and enabling high production.

Jayaraju’s presentation provided the details of the development process targeting micro-via fill of 60μm and 100μm deep vias, as well as the rigorous evaluation steps taken to make sure of its capability. He reported that this new process results in dimple depths of less than 10μm, and a void-free fill at a surface Cu thickness of less than 21 μm. Download the full paper.