Performance Gains in CMP Slurry for Advanced Semiconductor Nodes

December 07,2016

According to the 2015 International Technology Roadmap for Semiconductors (ITRS) report, the final report ITRS will issue, transistors will continue to scale until 2021. That’s five more years to take the industry from 14nm node down to the 5nm node, and it will take significant effort to get there. What’s more, new device architectures and technologies like 3D FinFETs, 3D NAND, and 3D packaging are also posing some challenges for tried-and-true manufacturing processes.

According to the 2015 International Technology Roadmap for Semiconductors (ITRS) report, the final report ITRS will issue, transistors will continue to scale until 2021. That’s five more years to take the industry from 14nm node down to the 5nm node, and it will take significant effort to get there. What’s more, new device architectures and technologies like 3D FinFETs, 3D NAND, and 3D packaging are also posing some challenges for tried-and-true manufacturing processes.

New Performance Requirements for Advanced Logic and Memory

For example, chemical mechanical planarization (CMP) processes for advanced logic and memory devices require more and varied nonmetal layer combinations that need highly tunable and dilutable CMP slurries, used in conjunction with matched CMP pads to achieve both technical and economic objectives.

In advanced-logic nodes, there are an increased number of CMP layers (e.g., 22-28 layers at 7nm compared with 12 layers for 45nm). These layers comprise different combinations, such as oxide, nitride, and polysilicon. Each layer needs to be polished at different rates, selectivity, and with tight process control.

Advanced memory applications are also incorporating additional CMP process steps (e.g., buff steps may be performed in a one-platen process with hard pads for improved defectivity and global uniformity after an etch step). There are enormous technical challenges to enable further scaling of current DRAM cell size. With the need for additional CMP steps, DRAM processes continue to demand higher removal rates to enable greater throughput and reduce overall cost of ownership (CoO).

In addition to low defectivity and reduced CoO, key performance drivers such as planarization efficiency, erosion, and dishing must have tight process control with-in-die and with-in-wafer uniformity.

Dow’s OPTIPLANE™ 2118 CMP Slurry

For Dow, these emerging requirements led to the development of a new family of dielectric CMP slurries  that uses state-of-the-art colloidal silica abrasives paired with advanced additives to offer high removal rates, planarization efficiency, and exceptionally low defect levels. One of these technologies is OPTIPLANE™ 2118 slurry, a low-abrasive, acidic pH silica slurry used for planarizing dielectric films in advanced CMP nodes. The enhanced CMP efficiency of this slurry is  primarily enabled by a unique formulation that promotes favorable particle/wafer interaction as illustrated in Figure 1

Figure 1: Silica abrasive-wafer interactions (a) without a charge-modifying additive and (b) with a charge-modifying additive.

Technical Article in Solid State Technology

We contributed to an article recently published in the September 2016 issue of  Solid State Technology magazine, where you can read more about new requirements for CMP processes, and see how Dow’s advanced slurry technology performs at advanced nodes.

View the article CMP slurry optimization for advanced nodes (PDF)