In Part 1 of this Connectivity series, we looked at current market trends driving advanced metallization processes for advanced wafer-level packaging (AWLP) applications. We also identified the issues that have arisen in trying to meet the ever-increasing metallization requirements, as emerging technologies join existing ones rather than replace them, contributing to wider process windows that will keep widening as next-generation devices come along. In Part 2 of this series, we will focus on the impact high density fan-out (HD FO), 2.5D and 3D packaging has on Cu plating requirements, and the role additives play in meeting metallization requirements.
3D packaging using through silicon via (TSV) interconnects have made their way into some products, such as stacked die memory applications for high-end computing and heterogeneous integration of disparate technologies on an interposer. However, it seems likely at this stage that adoption of TSVs will remain limited to a niche set of applications. Development efforts in TSV processes have turned to optimization to reduce cost while providing high performance and low power. This calls for high aspect ratio (HAR) vias, which allows for higher density at a reduced cost, as less Cu is required to fill the vias. HAR vias require µpillars to complete the interconnects.
For Cu pillars and µpillars, chemistry requirements include the ability to control the pillar shape, whether it’s a dome, flat or dished top. Bath levelers, suppressors and accelerators are additives used in the electroplating process to help control the final topography of the structure being plated, as well as control the speed, purity and quality of the final fill. The leveler additive, along with an optimized mix of other additives, allows you to shape the final topography of the filled structure by controlling solution flow and transport dynamics during plating (figure 1).
Figure 1. Understanding solution flow and transport dynamics in-via is critical to controlling relatively higher acceleration at center and less acceleration at edge of pillar
However, some levelers introduce impurities to Cu deposition, so their use requires a balance of achieving desired shape and ensuring reliability. The function of the suppressor is to act as a wetting agent. It wets the wafer surface quickly and aids in controlling plating thickness uniformity. A good wetting agent offers low surface tension and a low contact angle. Finally, the accelerator selectively increases the plating speed and makes bright depositions.
The ability to accommodate different pillar shapes is significant to the subsequent capping process and the size of the pillars. For example, if the Cu pillar diameter is small, it is more difficult to get enough solder on the top to form an adequate bump and reliable solder joint. And, if the pillar is also domed, the SnAg may be dropped or could run off during the solder reflow step. In this case, a dish or flat shape is preferred to form a reliable cap.
The tunability of pillar shape provides manufacturers with increased versatility for multiple applications. In addition, higher purity copper chemistry can reduce manufacturing costs by eliminating the nickel (Ni) barrier between the copper and solder elements, which is typically required in order to control topography and eliminate defects. A Ni barrier is generally used in high-reliability applications to prevent Kirkendall voids in the intermetallic compound (IMC) that forms between the Cu pillar and the SnAg bump (figure 2).
Figure 2. Nickel barrier can be used between copper pillars and tin-silver caps to eliminate micro voids caused by copper impurities.
However, if a copper chemistry has higher than typical purity, it is less likely to cause micro voids in the IMC. This eliminates the need for the Ni barrier step, thereby reducing manufacturing costs. As shown in Figure 3, void-free IMCs between Cu pillars and SnAg caps after solder reflow are possible to achieve with high-purity copper.
Figure 3. High purity copper eliminates micro voids and need for nickel barrier.
Dow’s scientists have achieved this tunability and purity described above with INTERVIA™ 9000 Copper chemistry. They also have their eyes on the future and are already at work on the next generation of Cu plating chemistry targeting “huge pillars” that measure 200µm x 200µm. This structure, targeting fan-out wafer-level packaging to be used for an application processor in a package-on-package configuration, requires plating speed of 25-30 ASD. As always, Dow Electronic Materials endeavors to remain on the cutting edge of advanced metallization requirements and enabling customers’ technologies.
Learn about the drivers for advanced packaging metallization in Part 1 of this series.