CMP Cost Reduction by Optimal Pad Selection

August 25,2015

Yield loss is widely recognized as the greatest cost in high-volume manufacturing (HVM) of commercial integrated circuit IC devices, and so significant cost-reduction comes from improving device yields. The design objective of the IKONIC™ family of chemical mechanical planarization (CMP) pads is to reduce defects, leading to higher wafer yields.

In addition, the IKONIC platform has the potential to extend pad lifetimes compared to legacy technologies, leading to direct savings in pad usage and indirect savings in reduced tool downtime for maintenance. In particular, when used with ceria slurries, the IKONIC 4000 pads have been developed to maintain consistent removal rates and profiles, which allow for longer use of the pad and thus reduce replacement costs. For example, the IKONIC 4250 pad for tungsten (W) processes and ceria-particle-based CMP was developed to achieve a higher removal rate pad to reduce polishing time and slurry consumption.

In addition, these new CMP pads are designed to meet a range of removal rate targets for throughput gains. These benefits make the IKONIC CMP pad platform an excellent choice for a wide range of advanced planarization applications.

Cost-reduction can also come about through coordination of technologies. For example, there are known interdependencies between pad materials, pad conditioning recipes, and slurry consumption in advanced CMP processes. Proper understanding of the chemical and mechanical interdependencies allows for fine-tuning of the pad material and the conditioning protocol such that higher removal rate can occur with reduced slurry consumption.

The general objective for CMP processing is to take a surface with uneven topography and make it as planar as possible, while leaving a very uniform and controlled film thickness across the wafer. Historically, soft pads are used to improve defectivity, though with the tradeoffs of lower pad lifetimes (and correspondingly greater relative costs) and reduced planarization. The design objective of IKONIC pads is to minimize this tradeoff and provide good planarization efficiency with low defectivity when used for finFET transistor formation.

Since CMP processes used in transistor formation influence the active performance of devices, uniformity control is a more critical challenge compared with CMP steps used in interconnect formation. Since transistor function is strongly influenced by the CMP process, every transistor, every die in the wafer, and every wafer has to be as uniform as possible. For this to happen, process control has shifted from die-level control to global control.

The IKONIC pad platform is a good example of how we design materials that address customer's critical problems. The platform raises the bar over prior offerings in terms of minimizing tradeoffs. However, as the industry continues to scale, new issues will emerge, and as with every generation, we will have to reset the clock and find new innovations.

In addition, these new CMP pads are designed to meet a range of removal rate targets for throughput gains. These benefits make the IKONIC CMP pad platform an excellent choice for a wide range of advanced planarization applications.

Cost-reduction can also come about through coordination of technologies. For example, there are known interdependencies between pad materials, pad conditioning recipes, and slurry consumption in advanced CMP processes. Proper understanding of the chemical and mechanical interdependencies allows for fine-tuning of the pad material and the conditioning protocol such that higher removal rate can occur with reduced slurry consumption.

The general objective for CMP processing is to take a surface with uneven topography and make it as planar as possible, while leaving a very uniform and controlled film thickness across the wafer. Historically, soft pads are used to improve defectivity, though with the tradeoffs of lower pad lifetimes (and correspondingly greater relative costs) and reduced planarization. The design objective of IKONIC pads is to minimize this tradeoff and provide good planarization efficiency with low defectivity when used for finFET transistor formation.

Since CMP processes used in transistor formation influence the active performance of devices, uniformity control is a more critical challenge compared with CMP steps used in interconnect formation. Since transistor function is strongly influenced by the CMP process, every transistor, every die in the wafer, and every wafer has to be as uniform as possible. For this to happen, process control has shifted from die-level control to global control.

The IKONIC pad platform is a good example of how we design materials that address customer's critical problems. The platform raises the bar over prior offerings in terms of minimizing tradeoffs. However, as the industry continues to scale, new issues will emerge, and as with every generation, we will have to reset the clock and find new innovations.