Breaking Trade-offs in the Planarization/Defect Balance

CMP Solutions for 10nm and Beyond

October 04,2016
Marty DeGroot, Global R&D Director, CMP Technologies, discusses CMP solutions for 10nm and other future nodes at the Strategic Materials Conference Korea in May 2016. Photo provided courtesy of SEMI.

As we discussed in a previous blog post, the requirements for chemical mechanical planarization/polishing (CMP) processes become increasingly challenging as the industry moves from the 28nm process node to 10nm and below. Existing materials and processes often cannot meet required defect levels across a 300 mm wafer when trying to planarize efficiently over extremely small features. Engineers need to carefully tailor the pad material, slurry formulation, pad conditioner, and process parameters in order to achieve the results they need.

CMP requirements are especially stringent for front-end planarization of finFET devices. The operation window is very narrow, both for processing a single wafer and for ensuring consistency across an entire batch of wafers and throughout the lifespan of a polishing pad. Consistency is critical because allowed defect levels are extremely low—on the order of single digit defect counts across a wafer. CMP polishing at the very front end of these devices is at or near the transistor, increasing the probability of dishing and critical defects. 3D stacked designs demand a high CMP removal rate, which places additional demands on the CMP process. However, there are ways to improve CMP processes for devices at and below the 10nm process node through innovative materials.

It is important to consider planarization on both a local and a wafer-level scale. Locally, both feature size and density play a role in choosing an appropriate polishing pad. Designs with different topography may dictate using a harder or softer pad. The critical step height for a given feature, defined as the onset of low area removal rate, depends on not only feature size but also the location and size of surrounding features. The distribution of features in a local area affects the difference between high versus low area removal rates and therefore the resulting planarization capability of a given pad material at the feature scale.

In general, harder pads provide greater planarization efficiency (PE) but also require greater contact pressure, which tends to cause a higher level of scratches and chatter marks on the wafer surface. There has traditionally been a trade-off between efficiency and defect rates that manufacturers have assumed is something they need to accept. Experimental pad materials in development hold the promise of achieving high PE, equivalent to that of hard pads, while reducing the amount of pressure needed to below that of even standard pads, resulting in better control over the CMP process.

Marty DeGroot, Global R&D Director, CMP Technologies, discusses CMP solutions for 10nm and other future nodes at the Strategic Materials Conference Korea in May 2016. Photo provided courtesy of SEMI.

As we discussed in a previous blog post, the requirements for chemical mechanical planarization/polishing (CMP) processes become increasingly challenging as the industry moves from the 28nm process node to 10nm and below. Existing materials and processes often cannot meet required defect levels across a 300 mm wafer when trying to planarize efficiently over extremely small features. Engineers need to carefully tailor the pad material, slurry formulation, pad conditioner, and process parameters in order to achieve the results they need.

CMP requirements are especially stringent for front-end planarization of finFET devices. The operation window is very narrow, both for processing a single wafer and for ensuring consistency across an entire batch of wafers and throughout the lifespan of a polishing pad. Consistency is critical because allowed defect levels are extremely low—on the order of single digit defect counts across a wafer. CMP polishing at the very front end of these devices is at or near the transistor, increasing the probability of dishing and critical defects. 3D stacked designs demand a high CMP removal rate, which places additional demands on the CMP process. However, there are ways to improve CMP processes for devices at and below the 10nm process node through innovative materials.

It is important to consider planarization on both a local and a wafer-level scale. Locally, both feature size and density play a role in choosing an appropriate polishing pad. Designs with different topography may dictate using a harder or softer pad. The critical step height for a given feature, defined as the onset of low area removal rate, depends on not only feature size but also the location and size of surrounding features. The distribution of features in a local area affects the difference between high versus low area removal rates and therefore the resulting planarization capability of a given pad material at the feature scale.

In general, harder pads provide greater planarization efficiency (PE) but also require greater contact pressure, which tends to cause a higher level of scratches and chatter marks on the wafer surface. There has traditionally been a trade-off between efficiency and defect rates that manufacturers have assumed is something they need to accept. Experimental pad materials in development hold the promise of achieving high PE, equivalent to that of hard pads, while reducing the amount of pressure needed to below that of even standard pads, resulting in better control over the CMP process.

Figure 1: Relative contact pressure for different types of CMP pads. Dow’s experimental pad materials demonstrate a reduction in contact pressure for high planarization efficiency.

The other issue to consider is planarization across an entire wafer. The usual tendency toward doming, where thickness is greatest at the center and lowest at the edges of a wafer, can be minimized by optimizing the mechanical properties of the pad. The pad conditioner also has a significant effect on pad morphology and texture, smoothing out microscopic variations in pad thickness and extending pad life. It is, therefore, critical to consider the interaction between the pad, the conditioner, and the slurry in order to keep performance consistent across a wafer and from wafer to wafer.

Dow is working with customers to bring our experimental polishing pads from the lab to the fab, optimizing the pads to work with real customer wafers and enable customers to better regulate the pressure on the wafer and meet their thickness control requirements. In this way, we will be ready with materials that can achieve the high PE and low defect rates that will be necessary to ensure reliable CMP for the next generation of finFET devices.

Download the Presentation: CMP Solutions for 10nm and Beyond

Editor’s Note: Dr. DeGroot presented on this topic at the Strategic Materials Conference Korea , May 18, 2016, in Seoul. The downloadable file is an excerpt of his conference slides.

Figure 1: Relative contact pressure for different types of CMP pads. Dow’s experimental pad materials demonstrate a reduction in contact pressure for high planarization efficiency.

The other issue to consider is planarization across an entire wafer. The usual tendency toward doming, where thickness is greatest at the center and lowest at the edges of a wafer, can be minimized by optimizing the mechanical properties of the pad. The pad conditioner also has a significant effect on pad morphology and texture, smoothing out microscopic variations in pad thickness and extending pad life. It is, therefore, critical to consider the interaction between the pad, the conditioner, and the slurry in order to keep performance consistent across a wafer and from wafer to wafer.

Dow is working with customers to bring our experimental polishing pads from the lab to the fab, optimizing the pads to work with real customer wafers and enable customers to better regulate the pressure on the wafer and meet their thickness control requirements. In this way, we will be ready with materials that can achieve the high PE and low defect rates that will be necessary to ensure reliable CMP for the next generation of finFET devices.

Download the Presentation: CMP Solutions for 10nm and Beyond

Editor’s Note: Dr. DeGroot presented on this topic at the Strategic Materials Conference Korea , May 18, 2016, in Seoul. The downloadable file is an excerpt of his conference slides.