The semiconductor industry is approaching a pivotal point where there will be no other way to achieve the performance, bandwidth and storage required of next-generation data centers and mobile devices without 2.5D and 3D integration technologies. As such, the entire ecosystem is collectively rolling up its sleeves and real work is being done to overcome the remaining challenges.
One remaining hurdle is assuring reliability of these devices, particularly for use in high-end server applications where part failures are much more catastrophic than in consumer mobile devices. Reliable device performance can be linked directly to materials used in advanced packaging assembly processes. In fact, reliability is such a concern for data centers that they are still exempt from RoHS requirements, and rely on legacy tin-lead for bumping processes. However, that exemption is set to expire in 2015, and solutions will need to be ready to put in place by then. This is a two-fold challenge with 3D ICs, which require fine-pitch microbumps that are difficult to achieve with standard solder materials, in addition to needing to be reliable. Until this is sorted out, 3D ICs are unlikely to be used to solve the data center bandwidth solution.
The Copper Pillar Advantage
Copper (Cu) pillars with tin-silver (SnAg) caps are emerging as a viable alternative to traditional bumping technologies. According to Prismark Partners, in 2013, bumped wafer production reached 14M wafers, of which only 6% were Cu/SnAg capped pillars. By 2018, the market research firm predicts that the total number of bumped wafers being produced will nearly double to 27M with 35% of those using Cu/SnAg capped pillars, and that’s not even including micro-bumps for TSV applications, which could increase the percentage further (Figure 1). Target applications include mobile devices, memory and high-end logic chips.
Figure 1. The wafer bumping market is expected to nearly double by 2018, with SnAg capped Cu pillars grabbing 35% of the market. (Courtesy of Prismark Partners LLC)
There are several technical reasons why transitioning from traditional solder bumps to Cu pillars capped with SnAg makes sense. In 100% of controlled collapse chip connection (C4) bump fabrication, reflowable solders collapse and spread during reflow. Therefore, to prevent bridging, bump pitch must be limited to 140µm. Additionally, the reduced bump stand-off height inhibits the flow of underfill. Alternatively, Cu pillars allow for tighter bump pitch, and because Cu is not reflowable it will maintain good stand-off height. Another advantage of Cu is its better thermal conductivity than solder, which is critical for high-speed and high-frequency devices, such as MPUs. Finally, compared with tin-based lead-free solder materials, Cu is a lower cost lead-free option.
Just Good Chemistry
Dow Electronic Materials is addressing the 2.5D and 3D IC reliability and process issues head on, making great strides in materials for, among other things, advanced packaging with bump plating for flip chip targeting not only reliability challenges but process challenges as well. The company has developed Cu and SnAg plating chemistries and processes that are exceptionally compatible and work well in tandem when used in Cu pillar applications.
First-generation Cu pillars use solder paste, but in 3D stacking, this will give way to Cu posts with SnAg caps as the preferred method. Because Cu is not reflowable, as previously mentioned, excellent thickness control within die (WID) is required for Cu pillars. In addition, maintaining tight control of total indicator reading (TIR) – the index for pillar top flatness – is critical to avoid dropping the tin silver solder bumps during the subsequent pillar cap reflow process.
Dow’s INTERVIA™ 8540 Cu chemistry features excellent WID with a mid-speed plating rate of ~2µm/min. This product has excellent physical properties and bonding reliability as a result of its pure deposition capabilities (~10 ppm total organic impurities). When combined with SOLDERON™ BP TS6000 SnAg chemistry, which features high-speed, uniform, fine-grain depositions with void-free reflow performance, the resulting SnAg-capped Cu pillars have uniform, void-free inter-metallic compound (IMC) layers (Figure 2).
A Seamless Process
An added benefit of Dow’s Cu and SnAg chemistries is that they demonstrate great compatibility, which translates into higher yield and mitigated manufacturing risk. Unlike other materials suppliers that supply either Cu or SnAg plating chemistry, Dow supplies both chemistries with a good understanding of how to optimize the process integration specifically for SnAg-capped Cu pillar applications. In the end, highly reliable Cu-SnAg interfaces are achieved.
Dow is currently developing a new generation of electroplating Cu, depicted as INTERVIATM 9000 Cu Chemistry in the table below, that satisfies all key design criteria including highly uniform Cu Pillars (WID < 5%); a flat pillar profile (TIR<5%); smooth surface morphology; and compatibility with SnAg capping (Table 1). Additionally, when used with the new Cu formulation, SOLDERON BP TS 6000 SnAg has demonstrated high-speed plating (>3µm/min); highly uniform SnAg deposits; void-free performance (X-ray); smooth surface morphology (as-plated and post-reflow) and a smooth, void-free interface with the Cu pillars.
Table 1. Characteristics of INTERVIA Cu and SOLDERON SnAg Chemistries for Cu pillars
These materials for forming Cu pillars with SnAg bumps is just one example of Dow’s efforts to develop compatible materials that enable reliability in emerging 2.5D and 3D packaging schemes.
Figure 2. Close-up of capped pillar shows