Will Fan-out Panel-Level Packaging Really Happen?

February 14,2017
Successful demonstration of fan-out panel-level packaging. Image courtesy and copyright Franhofer IZM.

Fan-out panel-level packaging (FOPLP) is currently one of the more controversial topics being discussed in the advanced semiconductor packaging world. As with many industry transitions, FOPLP has been a topic of discussion for some time. The push is being driven by perceived cost advantages and productivity benefits, as panels allow for parallel processing of more units during the same period of time. While a year ago the main concern was insufficient volume to justify the development of a panel-level supply chain, the increased adoption of fan-out wafer-level packaging (FOWLP) across various applications has changed that perception. Fan-out is already in production for wireless devices, power management units and radar devices, and it has been more recently adopted for application processing units in mobile devices, with other applications following closely behind. As the industry clamors for lower cost options, moving to panels seems to be a solution with high potential.

Still, the cost benefits are tightly tied to the package size and level of integration. Cost benefits are more likely to be achieved, in the near future, for smaller and low end packages requiring 10µm and above lines/spaces (L/S). For high-density packages, especially at 2/2µm L/S and below, technology development continues to be the main driver. There are still technical challenges that will have to be addressed before looking into cost benefits and potentially panel processing.

Yield is a significant issue, especially for mid and high-end packaging, and various organizations active in these segments are continuously working in improving that. Die shift, warpage, integration schemes are some of the main factors impacting yield. A number of outsourced semiconductor assembly and test providers as well as foundries are developing different methodologies to deal with die shift, as well as design structures that are less prone to warpage. Other concerns related to yield are the redistribution layers being incorporated into various FOWLP designs and the processing required to manufacture them. For example, the integrated fan-out package using a die-first approach, depending on the application, can have up to four layers of metal; as more layers are added, more processing will be required, which will be prone to additional challenges and could negatively impact not only the yield but also the cost of the package. The challenges of taking these designs from wafer level to panel level will be further increased.

With regard to materials-based challenges, chip package interaction, managing coefficient of thermal expansion (CTE) mismatch and balancing stress are already challenges for FOWLP. It stands to reason these challenges will be exacerbated by going to FOPLP due to the increase in processing area. While currently there is no industry standard on panel sizes, there are also variations in process steps compared to FOWLP and this can lead to new material needs. A few advanced packaging suppliers are leveraging their knowledge and infrastructure in panel processing and utilize the equipment and glass carriers from their touch panel and display lines for FOPLP. Given that the CTE of glass is adjustable, the use of glass carrier may help alleviate the warpage and stress challenges or create new material requirements for the molding compound and die attach materials.

Spin-on dielectric is commonly adopted in FOWLP but given the size and rectangular shape of the panels in FOPLP, dielectric dispense methods such as slit coating and dry film lamination are currently being investigated. Besides optimizing the mechanical and electrical properties of the dielectric materials, materials suppliers are now faced with an additional challenge in ensuring coating uniformity with two very different dispense processes. Although existing dielectric materials show feasibility in enabling FOWLP, new materials will likely be needed to support FOPLP and the material requirement will be highly dependent on the associated process infrastructure set up by the packaging houses. And given the industry trend towards the adoption of copper pillar for enabling Package-on-Package (PoP) and 3D Packaging in general, increased plating speeds for pillar and RDL metallization will play a role in influencing the overall cost benefits with FOPLP.

Many predict that, as with many innovative package technologies, a specific application or applications will drive such a significant move. Transitioning to FOPLP will happen if the industry supply chain can develop a comprehensive solution to deal with all these challenges. We look forward to collaborating with our customers to ensure we are ready with materials suited to the task whenever the transition comes to pass.

Successful demonstration of fan-out panel-level packaging. Image courtesy and copyright Franhofer IZM.

Fan-out panel-level packaging (FOPLP) is currently one of the more controversial topics being discussed in the advanced semiconductor packaging world. As with many industry transitions, FOPLP has been a topic of discussion for some time. The push is being driven by perceived cost advantages and productivity benefits, as panels allow for parallel processing of more units during the same period of time. While a year ago the main concern was insufficient volume to justify the development of a panel-level supply chain, the increased adoption of fan-out wafer-level packaging (FOWLP) across various applications has changed that perception. Fan-out is already in production for wireless devices, power management units and radar devices, and it has been more recently adopted for application processing units in mobile devices, with other applications following closely behind. As the industry clamors for lower cost options, moving to panels seems to be a solution with high potential.

Still, the cost benefits are tightly tied to the package size and level of integration. Cost benefits are more likely to be achieved, in the near future, for smaller and low end packages requiring 10µm and above lines/spaces (L/S). For high-density packages, especially at 2/2µm L/S and below, technology development continues to be the main driver. There are still technical challenges that will have to be addressed before looking into cost benefits and potentially panel processing.

Yield is a significant issue, especially for mid and high-end packaging, and various organizations active in these segments are continuously working in improving that. Die shift, warpage, integration schemes are some of the main factors impacting yield. A number of outsourced semiconductor assembly and test providers as well as foundries are developing different methodologies to deal with die shift, as well as design structures that are less prone to warpage. Other concerns related to yield are the redistribution layers being incorporated into various FOWLP designs and the processing required to manufacture them. For example, the integrated fan-out package using a die-first approach, depending on the application, can have up to four layers of metal; as more layers are added, more processing will be required, which will be prone to additional challenges and could negatively impact not only the yield but also the cost of the package. The challenges of taking these designs from wafer level to panel level will be further increased.

With regard to materials-based challenges, chip package interaction, managing coefficient of thermal expansion (CTE) mismatch and balancing stress are already challenges for FOWLP. It stands to reason these challenges will be exacerbated by going to FOPLP due to the increase in processing area. While currently there is no industry standard on panel sizes, there are also variations in process steps compared to FOWLP and this can lead to new material needs. A few advanced packaging suppliers are leveraging their knowledge and infrastructure in panel processing and utilize the equipment and glass carriers from their touch panel and display lines for FOPLP. Given that the CTE of glass is adjustable, the use of glass carrier may help alleviate the warpage and stress challenges or create new material requirements for the molding compound and die attach materials.

Spin-on dielectric is commonly adopted in FOWLP but given the size and rectangular shape of the panels in FOPLP, dielectric dispense methods such as slit coating and dry film lamination are currently being investigated. Besides optimizing the mechanical and electrical properties of the dielectric materials, materials suppliers are now faced with an additional challenge in ensuring coating uniformity with two very different dispense processes. Although existing dielectric materials show feasibility in enabling FOWLP, new materials will likely be needed to support FOPLP and the material requirement will be highly dependent on the associated process infrastructure set up by the packaging houses. And given the industry trend towards the adoption of copper pillar for enabling Package-on-Package (PoP) and 3D Packaging in general, increased plating speeds for pillar and RDL metallization will play a role in influencing the overall cost benefits with FOPLP.

Many predict that, as with many innovative package technologies, a specific application or applications will drive such a significant move. Transitioning to FOPLP will happen if the industry supply chain can develop a comprehensive solution to deal with all these challenges. We look forward to collaborating with our customers to ensure we are ready with materials suited to the task whenever the transition comes to pass.