Building on last year’s focus on the development of a smart, connected world, this year’s theme, “IMPACT on Intelligent Everything,” will dive deep into future technology trends for smart applications, robots, drones, autonomous vehicles, artificial intelligence and IoT devices. Held in conjunction with TPCA SHOW 2017, the International Microsystems, Packaging Assembly and Circuits Technology (IMPACT) conference, organized by IEEE CPMT-Taipei, iMAPS-Taiwan, ITRI and TPCA, is the largest gathering of IC packaging and printed circuit board (PCB) professionals in Taiwan.
Dow Electronic Materials’ experts are once again honored to join the ranks of renowned researchers and academia participating at IMPACT 2017. The company will present its latest research findings and process breakthroughs related to eliminating tin whiskers in PCB manufacturing and meeting the requirements for ever-tightening features sizes for high-density interconnect (HDI) applications. During the conference, Dow scientists will present the following two papers:
#1 Studies of Tin Whisker Growth under High External Pressure (Download Paper)
Tin whiskers are recognized as a much more serious reliability
threat to lead-free electronic components or products due to the
implementation of the European Directive on restrictions of hazardous
substances (RoHS) legislation in July 2006. This position is
exacerbated by the trend for increased sophistication and
miniaturization in electronics. Although the tin whisker growth
mechanisms have been studied for more than 50 years, the tin whisker
nucleation and growth mechanisms still have not been fully understood.
Besides, the significant research work focused mainly on understanding
of the whisker formation as a consequence of inner surface stress
relief. Little theoretical or systematic work has been carried out to
understand the formation of whiskers driven by external mechanical
stress, such as the high external mechanical stress in press-fit
Press-fit connection is a solderless technology for making reliable electronic joints. Modern press-fit compliant solution provides many advantages when compared with soldering, such as solderless, low thermal stress, better reliability, lower cost, etc., making it a popular interconnect technology. It is reported that press-fit connectors have begun to dominate high-end connector applications for telecommunications, computer printed circuit boards (PCBs) and automotive electronic modules. The press-fit technology allows for the insertion of a press-fit pin (male) into a plated-through hole (PTH, female) in a printed circuit board (PCB) to establish a cold welded interconnections autonomously without using solder, especially when tin plating is used for at least one of both contact partners (pin/hole). The press-fit compliant pins having an elastic press-in zone deform when inserted into a PTH and sustain a permanent high contact normal force between the compliant pin and PTH. The external pressure applied by the compliant press-fit zones during and after performing the press-in process increases the tendency to create tin whiskers especially for pure tin finish. These whiskers grow on much shorter time scales than whiskers caused by the stress introduced by intermetallic phase growth. Furthermore, the technology trend towards higher density connector solutions (closer pin to pin/hole to hole distance, much higher external pressure) further increases the risk of electrical short-circuit due to the formation of tin whiskers.
In this study, a series of factors that may affect whisker growth on electroplated tin coatings under external pressure were studied, including storage time, coating thickness, grain structure, loading, ball diameter, etc., to improve the understanding of the external pressure-induced whisker growth mechanism. It was found that longer storage time, thicker coating (< 3 μm), higher loading and higher pressure will give more and longer whiskers. Equiaxed grain structure with moderate grain size can disperse external compressive stress more efficiently, thus mitigating whisker growth.
#2 A Novel Electroplating Technology with Leveling Minimum Surface Deposition for HDI Application ( Download Paper)
Electrolytic copper micro via filling is an enabling technology, prominently used in today’s manufacture of high density interconnect (HDI), to be driven by the needs for faster speed, smaller dimension and higher performance versus communication and electronic devices; and also in response to the evolution of the wafer manufacturing technology, which eventually required smaller and smaller pitch BGA substrate for packaging, more dense I/O counts increase transmission efficiency, and minimize routing reduce signals disturbance. Thus, the trend of circuits on HDI boards will tend to be constructed by high density stacked vias and smaller vias. And the increasingly difficult micro via geometries must be filled without void and skip plating over million vias, while maintaining plating rates capable of delivering production throughputs. This paper describes the study on the factors affecting copper electroplating for micro via filling, and developing new plating formula with great surface leveling, thinner copper deposit thickness for direct current (DC) copper process for HDI application....More
Playing off the popularity of the Internet of Things and the
development of technologies required to support wearable devices and
smart home applications, the IMPACT-IIAC 2016 Joint Conference, which
took place Oct. 26-28 in Taipei, Taiwan, was aptly themed, “IMPACT on
the Next Big Things,” and included panel sessions, invited talks,
industrial sessions and paper presentations on topics related to
accelerating manufacturing and commercialization of smart, connected
devices. Please check links below to download or read more
#1 Next Generation Electrolytic Copper Plating Process for HDI Applications (Download Paper) Best PCB Paper Award
Novel and robust electroplating formulations are required to meet the challenging demands for High Density Interconnect (HDI) applications. These requirements include (A) Thinner and uniform surface copper (B) Void-free electrodeposition of copper in Filled blind micro-vias (BMV) and (C) Higher throwing power (TP) in high aspect ratio through holes. A Direct Current (DC) plating process was developed to meet these requirements...More
The new product provides via filling with higher throwing power in through holes while maintaining high plating rates, enabling high production throughputs. The plating process was evaluated as a function of a variety of process variables including eductor distance, solution flow rate, current density and additive concentrations. The test panels used were 1mm thick with 60 µm deep vias on one side and 100 µm deep vias on the other side. The panels included through holes of 0.15mm and 0.25 mm diameters and micro-via diameters between 75-150 µm. The test panels were processed through Electroless Copper prior to electroplating which was performed in 60 Liter vertical in-line plating equipment using insoluble anodes.
An optimum flow rate of 25 L/min was used for better via fill and throwing power. The eductor was positioned at 1, 2 and 3 inches away from the test panel. The optimum distance was determined to be 1 inch to achieve filled vias with dimples less than 10 µm. Plating tests were also carried out as a function of current density (15, 20, 25 and 30 ASF). Dimple depth gradually increased with increasing current density from 15 to 30 ASF but still remained below 10 µm in depth. Throwing Power greater than 80% was achieved in 0.15 mm and 0.25 mm diameter through holes. The plating bath was cycled to 200 Ah/L to evaluate the performance.
This paper will discuss the development of a novel next generation product for micro-via fill (60 µm and 100 µm deep vias). Dimple depths less than 10 µm, void-free fill at a surface Copper thickness of less than 21 µm can be achieved with this next generation product.
#2 A Potential Silver Catalyst System for Next Generation of Electroless Cu Process as a Palladium Substitution (Download Paper)
Electroless plating of copper onto insulating substrates is a process broadly applied in the electronics industry for manufacture of printed circuit boards and decorative plating of plastic parts for automotive or consumer appliance. The key step involves surface activation of the dielectric surface for deposition in electroless copper bath. Palladium catalyst, either in its ionic form or metallic form, is most widely used for this purpose. However, the high and volatile unit metal price causes the catalyst solution to be the most expensive part among the electroless process. The economic pressure imposed on manufacturers and consumers would be the major driving force for developing an alternative catalyst system with lower cost....More
Previously we have introduced the innovative nano-silver catalyst
system such as the physical properties, catalytic performance on
conventional electroless copper deposition, and reliability
performance in copper-copper interconnects area.  In this paper,
comparison of silver catalyst with traditional palladium catalyst for
MHC process will be described. Further study on deposition profile,
microvia coverage and morphology, and reliability performance with
liquid-to-liquid thermal shock will be illustrated. In the last
section, the concerns on silver migration with silver catalyst
applications on printed circuit board will be discussed.
#3 New Immersion Gold Product for Uniform Au Thickness Distribution (Download Paper)
Electroless Nickel Immersion Gold (ENIG) is one of the important final finish techniques that is used in the printed circuit board industry. Despite its relatively expensive cost compared to other final finishing processes such as OSP and immersion Tin etc., ENIG has many advantages. The low reactivity of Au can protect the underlying Ni and Cu surfaces from oxidation and keeps the board suitable for long storage time. It provides excellent surface planarity suitable for soldering, especially for tiny parts such as BGA and Flip-Chip, and the surface remains solderable even after multiple reflow cycles. It is useful for contact surfaces such as membrane switches and contact points and may also be used for wire bonding...More
The Immersion Gold (IG) bath provides the protective Au layer after the Electroless Ni (EN) process following the below equation: 2Au+ + Ni → 2Au + Ni2+. As an electrochemical process, the deposition rate (or Au thickness per unit of time) is highly dependent on the redox potential of Au+ and electropotential of the Ni surface. The former can be considered as a fixed value in a Au plating solution while the latter will vary depending on the design of boards (pad size, connection of pad to the inner-layer Cu, etc.). The differences of surface potential, or so-called galvanic effect, makes the deposition of Au non-uniform, which may influence the properties of the board in many aspects. For example, chromatic aberration of the Au surface appears and some of the extremely thick Au pads may appear as red color; solderability may become uneven across all pads; and Au may be wasted due to the poor gold thickness distribution. More seriously, the galvanic effect may cause Au skip-plating, or black Ni because of Ni over-dissolution on specific pads, resulting in the solderability problem.
Our new immersion gold technology can effectively reduce the galvanic effect by introducing a new chemical system. The electropotential differences were minimized among pads with various surface areas or connected to different inner-layer copper areas thus providing a uniform gold deposition. Meanwhile, the plated Au thickness can be steadily increased from less than 1 microinch to 3 microinches and metallic lustre of the Au surface remained normal, from the pale yellow of thinner Au to the lemon yellow of thicker Au.
#4 High Performance Cyanide-free Immersion Gold (Download Paper) Best PCB Paper Award
Printed circuit board requires surface finishes to be applied to functional areas prior to assembly operations. There are a number of final finishing technologies available in the market. Electroless Nickel Immersion Gold (ENIG) is a widely used surface finish which is suitable for use as a solderable and aluminum wire-bondable finish, and also a contact surface for metal contact switches. It is because of its excellent solderability and ability to resist corrosion. Conventionally, cyanide containing gold salt for example potassium gold cyanide, is used as gold source in the immersion gold bath. It is well known to have excellent bath stability, easy bath control and high repeatability performance. However, environmental, health and safety (EHS) concerns arose on this process. Potassium gold cyanide is well-known as a highly toxic substance. It may be fatal if swallowed, contacted or inhaled. It is also highly toxic to environment especially to aquatic life. Mishandling of the gold salt or the gold bath may lead to release of cyanide gas which causes environmental issues....More
As green material and process safety are the future trend in the industry, development of cyanide free immersion gold process is one of remarkable research topics. However, up to now, there is only limited amount of cyanide free immersion gold bath available in the market. The challenge is to maintain good bath stability with continuous operation when getting rid of cyanide to complex the gold ions.
In this paper, a novel cyanide free immersion gold bath will be described which can be applied in ENIG process for continuous operation. Beside free of cyanide, the bath characteristic can be operated at about 45°C and neutral pH. This operating temperature is much lower than traditional cyanide containing immersion gold bath which operated at about 80°C. This bath can solve the EHS concerns and serve for energy saving as well. The bath was stable with no significant change in plating rate after long time idling. Most importantly, the plating performance is equivalent to conventional immersion gold bath.
#1: Next Generation Plating Process for Filling Blind Micro-vias (Download Paper)
This paper describes the study of a new pattern plate, direct current (DC) electrolytic copper plating chemistry for IC package (PKG) application. The new chemistry shows good via-filling performance and good pattern plate uniformity together with thinner surface copper deposit. Also it shows excellent thermal reliability and good deposit physical properties. The new chemistry delivers high quality and high reliability for pattern plate for IC package application.
#2: Ionic Palladium Catalyst Process for Electroless Copper Metallization (Download Paper)
This paper describes the development of a new ionic palladium catalyst, CIRCUPOSIT™ 6530 Catalyst, along with a tartrate-based horizontal electroless copper bath, CIRCUPOSIT™ 6550, to meet the performance demands of high-density-interconnect (HDI) and packaging (PKG) substrates in horizontal electroless copper plating. Implementation of the new ionic catalyst process is demonstrated through excellent coverage and reliability performance of through holes and microvias on HDI and PKG substrates following processing in horizontal equipment, as well as peel strength on low profile dielectric materials in the semi-additive process. Results also showed that the new CIRCUPOSIT™ 6530 Catalyst demonstrated stable performance during customer qualification.
#3: High Performances PPR Copper Plating for High Aspect Ratio Boards (Download Paper)
Multilayer boards, which are widely used in professional electronics such as sever, communication, medical and military equipments, trend to increase board thickness/layer counts (up to more than 10 mm/40 layers) and aspect ratio (up to more than 25:1). Accordingly, it becomes more and more difficult to plate copper into the through holes with an acceptable deposit. To meet these demands, a new generation of high performances PPR copper plating process has been developed, designed for use with soluble anodes and simple rectangle waveforms in vertical application. The new PPR chemistry demonstrates an excellent and stable throwing power up to a tested bath life of more than 200 AH/L. Neither a continuous carbon polish nor the frequent carbon treatment is required during operation. Meanwhile, it is easy to restart after idling with no need for a long dummy process. Effects of substrate, waveform on throwing power performance, the process capability to pattern and blind vias plating are also discussed in this article.
#4: Next Generation Copper Pattern Plating for IC Package Application (Download Paper)
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