August 01, 2019
Later this month, the Northern California Chapter of AVS (NCCAVS) CMP Users Group and the Center for Advanced Materials Processing (CAMP) at Clarkson University will host the 23rd International Symposium on Chemical-Mechanical Planarization (CMP) – also commonly known as CAMP. The 2019 event will bring industry and leading scientists together at the High Peaks Resort in Lake Placid, N.Y., from August 11-14, 2019, to discuss the latest advancements in CMP.
This highly technical conference will look at the challenges and latest developments in CMP with a solid program of speakers from leading equipment and device manufacturing firms. At the symposium, scientists from DuPont Electronics & Imaging will offer multiple presentations focused on materials challenges and the company’s latest approaches to addressing them. The topics will include:
A fundamental look at some emerging CMP challenges: High planarization efficiency dielectric and high removal rate metal
John McCormick*, Mike Mills, Todd Buley, Marty DeGroot
Monday, August 12
Session II, 10:10 A.M.
High planarization efficiency (PE) dielectric CMP challenges continue to grow based on the technology roadmap for NAND, with layer count proceeding from 32 to 64, and now past 128 layers. An alternative process utilizing large-area etch to reduce the resulting mesa has emerged as an alternative “non-CMP” removal step, where CMP is relegated to “cleaning” up the fringes left over after etching. The fundamentals of planarizing this large-length scale (> 1000 µm) dielectric structure will be discussed, relating our current understanding of the interactions between pad, slurry, conditioning, and the polishing process.
Metal polishing time at P1 for thick metal layers has been identified as a current bottleneck in reducing overall CMP metal process cost. Significantly reducing the polish time for P1 would balance out the platen throughput and position this CMP process more economically against the previously mentioned etch process. This session will also look at the fundamentals of significantly increasing the metal removal rate (RR).
Reduced post-CMP ceria contamination levels by the inclusion of a pad buff cleaning step
Paul Bernatis*, Jhih-Fong Lin, Wayne Huang, Fengji Yeh, Katie Gramigna, Chi Yen
Tuesday, August 13
Session VI, 4:25 P.M.
The increased complexity of leading-edge logic devices, along with the implementation of 3D geometries in memory, have been two drivers for the growing number of CMP steps being used in advanced semiconductor manufacturing. Aggressive slurries with high removal rates have been adopted by high volume manufacturers (HVMs) to keep up with the demanding productivity requirements.
Positively charged ceria and silica slurries are in the class of very fast slurries that are used for planarizing dielectrics such as TEOS and poly-silicon. To achieve a high removal rate, the slurries form strong chemical and electrostatic bonds to the dielectric surface. This makes removal of the slurry residues following CMP particularly challenging. DuPont’s EKC Technology has developed formulated cleans, such as EKC™ PCMP2110, that leave very low levels of residues approaching 1e10 atoms/cm2 when applied in a traditional brush box on the CMP tool. However, an ultimate goal of many HVMs has been to fully clean the wafer within the footprint of the CMP tool, which means ceria levels need to be below 1e10 atoms/cm2.
This talk describes an approach using pad buffing to reduce post-CMP defect levels, including examples in which buffing has been done on a platen on the CMP tool or in a pre-clean module. Factors that control the residue levels include pad hardness, rotation speed and pressure. Optimized tool conditions will be described where, with the EKC™ PCMP2110 chemistry, final defect levels are 30 to 60 percent lower than when the clean is done in the brush box alone.
Design of slurry chemistries for chemical mechanical planarization of nonmetals used in front-end-of-line semiconductor fabrication
Murali G. Theivanayagam*, Naresh Penta, Yi Guo, Robert Auger
Wednesday August 14
Session VIII, 10:50 A.M.
CMP is one of the key unit operation steps to planarize uneven gap fill structures in order to build and isolate transistors, and to build metal connections and contact plugs during fabrication of semiconductor devices. Slurries, commonly containing metal oxide nanoparticles as an abrasive agent, are one of the important consumables needed for CMP. In the front end of line of a device, polishing of nonmetals such as silicon dioxide, silicon nitride and silicon films (amorphous and polycrystalline) is performed for shallow trench isolation, FinFET gate structures, dummy poly gate openings, self-aligned contacts, and other features.
Both selective and non-selective CMP steps are used to achieve desirable integrated structures and are enabled by designing appropriate slurry chemistry. This presentation will describe the physical and chemical aspects of the design of colloidal silica-based slurries with unique selectivity to silicon dioxide, silicon nitride and silicon films (amorphous and polycrystalline).
Ask a DuPont Electronics & Imaging Expert
If you plan to attend the upcoming 23rd International Symposium on CMP and have questions for our experts, we’d love to talk to you. Please contact us here in advance so we can arrange a time to meet up on site. We look forward to sharing our knowledge and learning from our peers at CAMP 2019!