Why wafer bumping needs interface between metal layers

Wataru Tachikawa

Global Marketing Manager for Metallization, Advanced Packaging Technologies, Dow Electronic Solutions

March 15, 2016


There’s no doubt about it, when it comes to the latest in wafer-level packaging requirements, thin is in. We all know about the transformation of the early cellphones of the ‘80s and 90s into thinner cellphones and eventually smartphones. Along the way, the addition of new functionality, such as cameras, more processing power and more memory, and the need for larger battery capacity slowed or even reversed the drive for thinner devices until the next technology advancements came along. Advances in wafer bumping technology have been a large part of this transformation. To jam all the functionality in today’s smartphones and still maintain the thinness calls for extremely thin WLPs, PoP and potentially 2.5D-IC stacks, which calls for smaller solder points and more of them. Fan-out wafer level packaging is emerging as a solution, however, bumped packages are currently the HVM approach.

These tight pitch requirements of today’s devices are leading the industry away from traditional C4 bumping technologies to copper (Cu) pillars with tin-silver (SnAg) caps. According to Prismark Partners, by 2018, the total number of bumped wafers being produced is expected to nearly double to 27 million, with 35 percent of those using Cu/SnAg capped pillars. That’s not even including micro-bumps for TSV applications, which could increase the percentage further (see Figure 1)

Figure 1: Bumped Wafer Production by Technology. Courtesy of Prismark Partners LLC


When selecting materials that will result in high-yield, reliable electroplated Cu pillar and Cu µpillar capped structures, it’s important to consider the interface between metal layers, particularly as Cu pillar cap diameters shrink to µpillar dimensions (<30µm diameter). Additionally, interfacial properties and intermetallic compounds (IMCs) must be understood and controlled. The plating chemistry has significant influence on the compatibility of each layer, as well as control of IMC-growth, micro-void formation and overall stack reliability. With SnAg-capped Cu pillars, the IMC region is typically larger than would be observed with traditional SnAg C4 bumps on nickel under-bump metallization (see Figure 2).

Figure 2. SEMs and x-ray inspection of 75 µm SnAg C4 bump on a Ni substrate (left) and 20 µm SnAg-capped Cu micropillar (right)


The IMC interface is needed to provide a mechanically strong metallurgical bond and is necessary for creating the interconnection. Controlling the thickness of the IMC is important, however, to minimize potential brittleness or voids that could create reliability issues during the assembly process and over the life of the end-use device. Minimizing or eliminating impurities in the electroplated copper is imperative to achieving an acceptable IMC with SnAg, especially as it relates to preventing formation of micro voids. In addition, the composition of formulated additives in the plating baths for both copper and SnAg plays an important role in controlling the IMC formation.

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