Cellphones have changed considerably in the past 20 years, both in terms of form and function, as the market has exploded globally. Today’s smartphone looks and acts very little like a 1990s cellphone, inside or out. Most sport a different manufacturer’s name, and they have really become portable computers; the function of making phone calls has become secondary. The stylistic and functional changes are obvious to all, but the technology inside has undergone an equally extensive transformation.
Development of cellphone technology has been a major driver for advances in semiconductor packaging and printed circuit board (PCB) design, and via fill plays an important role. PCBs in the 1990s were fabricated with through holes with conformal copper plated. This first-generation, one-layer structure only allowed for connections to the outer layer on the top or bottom surface of the PCB.
With the advent of smartphones in 2010, the “any layer structure” came of age, with multiple stacked microvias, many blind or buried, throughout the layers of the PCB to provide the ultimate flexibility in design. This technology, however, did not develop overnight but in a series of generations over about 15 years.
The via filling process begins with electroless Cu plating of a seed layer to metallize the sidewalls, followed by electroplating to fully fill the via with Cu. The first generation of Cu microvias suffered from several issues, including voids in deep vias, sunken dimples at the top of the via, or inconsistent filling, all of which affected reliability. The need for a relatively thick (30µm or more) layer of Cu over the surface of the board to ensure sufficient via filling posed a challenge to PCB design.
As cellphones have incorporated more functionality into ever-thinner devices, plating thickness becomes one more barrier to achieving the goal of lighter, thinner, faster electronics. Every step counts when trying to reduce the overall thickness of the PCB.
The second generation of microvia fill achieved several important advances: decreasing the required plating thickness, improving the quality of through via plating, and enabling patterned plating for stacked, blind or buried microvias, which allow for higher-density packaging. These improvements led to huge increases in adoption of microvias in the PCB industry, especially in the cellphone market.
By 2013, plating thickness had decreased considerably, to around 15µm, but at the expense of worse through-hole plating capability. The next generation focused on improving through-hole plating while keeping plating thickness to a reasonable level. This fourth-generation process is gaining market traction globally.
The most recent generation of microvia fill is in development as of mid-2016. This process combines the best features of all the previous generations: consistent via fill, thinner plating thickness, excellent through-hole plating capability, and complete flexibility in patterning multiple stacked vias.
The newest microvia plating process adds another important advantage, one that improves throughput. Standard Cu electroplating requires first depositing a thin strike copper layer before filling the entire via to acquire a wide process window in term of stable fill Cu performance and field process management. Dow has achieved one-step electrolytic via fill, eliminating the need for a strike copper layer while retaining excellent performance. While this fifth-generation process is still in development, the combined advantages over previous generations should allow it to eventually become the process of choice for high-density PCB boards with multiple stacked microvias.