Semiconductor Packaging Materials

Through Silicon Via Copper


Production-proven Through Silicon Via Chemistries Meet High Aspect Ratio Requirements

Years of experience and success in electroplating damascene copper have helped DuPont Electronics & Imaging bring leading-edge copper through silicon via (TSV) chemistries to the advanced packaging market. Our production-proven, three-component copper solutions enable even the most challenging TSV aspect ratios due to:

  • High purity copper
  • Gap-free performance during bottom-up fill
  • Fast plating speeds
  • Elimination of Cu overburden

As TSVs become a mainstream interconnect technology used in memory stacking, CMOS image sensors, MEMS devices, and 2.5D interposer architectures, DuPont remains at the forefront, optimizing offerings to meet TSVs evolving needs.

Product Lines

  • Interlink™ 9200 Copper
  • Through silicon vias (TSVs) are vertical electrical interconnects formed using wafer etch processes and filled with either Cu or tungsten. First introduced in compound semiconductor applications, TSVs are also used in MEMS devices and CMOS image sensors, to create 3D memory stacks, and 2.5D interposer architectures, driven by high-performance computing needs.

  • Our Cu chemistries for TSV production are designed to meet requirements for leading edge TSVs with a 10:1 aspect ratio. This requires high purity, faster plating speeds without voids, gap-free bottom-up fill with minimal Cu overburden to reduce the need for chemical mechanical planarization processes.

  • DuPont delivers a full portfolio of packaging and assembly materials for the semiconductor industry. Click here to view a short video of our comprehensive offerings.

Semiconductor Packaging Materials

  • Through Silicon Via Copper

    Through Silicon Via Copper

    Years of experience and success in electroplating damascene copper have helped DuPont bring leading-edge copper TSV chemistries to the advanced packaging market.

  • Copper Pillar Plating

    Copper Pillar Plating

    Our production-proven Cu pillar formulations work in perfect harmony with our under-bump metallization (UBM) and tin-silver capping chemistries, to provide a seamless solution for all your Cu pillar needs.

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  • Solder Bump Plating

    Solder Bump Plating

    DuPont’s award-winning Solderon™ BP electroplating chemistries are a reliable alternative to tin-lead alloys for all wafer bumping applications.

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    Indium plating chemistry designed for low-temperature solder plating processes used in advanced wafer-level packaging for emerging applications that are sensitive to temperature.

    HVM-proven tin-silver plating chemistry for lead-free, fine-pitch solder bump applications with industry-leading process versatility.
  • Under Bump Metallization

    Under Bump Metallization

    We offer a production-proven electroplating nickel chemistry tailored to meet a variety of UBM process needs

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  • Bump Plating Photoresists

    Bump Plating Photoresists

    DuPont offers positive- and negative-tone photoresists designed to meet the tight pitches and varied topographies of today’s semiconductor advanced packaging applications.

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    Wafer-level packaging dry-film photoresist solutions for 3DIC, fan out, bumping, copper pillar and redistribution applications.

    DuPont offers liquid bump plating photoresists, along with associated ancillaries, that are ideally suited for wafer-level packaging applications using single-spin coating.
  • Copper Redistribution Layer

    Copper Redistribution Layer

    DuPont Electronics & Imaging copper chemistries for redistribution layers (RDLs) are ideally suited to today’s high-density requirements for wafer level packaging applications.

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  • Packaging Dielectrics

    Packaging Dielectrics

    Look to DuPont for packaging dielectric formulations that have the mechanical properties, high resolution, low-temp curing, easy processes, and superior reliability needed to protect your advanced WLP.

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