Polymers weave a vital thread for advanced packaging

August 30, 2019

The role of polymers in advanced packaging continues to grow as new and emerging markets and applications bring increased performance demands on devices. We recently sat down with Lucy Wei, global marketing manager focused on advanced semiconductor packaging polymers for DuPont Electronics and Imaging (right), to discuss this topic, including the market drivers addressed by polymeric materials, criteria for their selection, and what’s next on the horizon.

Q. What are the technological trends associated with polymeric materials in          advanced semiconductor packaging?

With the era of 5G and artificial intelligence fast approaching, many devices will be needed for use in high-speed/high-frequency (HS/HF) applications – which, in turn, require low-loss polymeric materials. These materials must be able to provide low electrical loss at a wide range of frequencies and be stable over a wide thermal and moisture range. Another trend is the need for polymer materials with high thermal conductivity. This is a key requirement for all devices going forward, especially those deployed for data centers and high-performance computing.

Q. What are the primary criteria that electronic manufacturers are using to select polymeric materials for HS/HF applications?

The primary function for an IC package is to protect the die from the environment, to provide electrical connections for the die, and to provide insulation for the copper lines and assembly input/outputs (I/Os) in substrates and circuit boards. Polymeric materials play a critical role in protecting the die from damage and offer good performance in a variety of environments. Electronics manufacturers look for materials that provide these four primary benefits:

  1. Electrical insulation – the materials need to help devices reduce signal loss with low leakage current and high breakdown voltage
  2. Mechanical protection – polymeric materials must have high fracture toughness with good elongation and tensile strength, both to help minimize stress during multilayer build-up and to enable the package to survive harsh conditions such as drops, thermal cycles and warpage
  3. Environmental resistance – polymers must have properties that help the package resist damage from chemicals used in the chip packaging processes, as well as from any moisture that electronic devices may encounter
  4. Good physical properties – materials with good thermal conductivity are needed to help dissipate heat generated in local spots and protects components, while providing low coefficient of linear thermal expansion (CTE) to reduce mismatch between silicon chips and organic materials so that advanced packages can survive temperature changes in real-world use (and, for optical device packages, manufacturers look for low loss in the near-infrared (NIR) spectrum)

These criteria remain the same but are more important than ever with the specific demands and challenges that HS/HF applications place on electronics devices.

Q. What are the main concerns and challenges for polymeric materials with respect to 3D through-silicon via (TSV) technology?

Currently used primarily for stacked memory and stacked CMOS image sensor (CIS) packages, 3D TSV demand is being driven mainly by the memory market. The high demand placed on memory in HS/HF and 5G applications necessitates thinner and thinner memory packages.

Current high-bandwidth memory (HBM) uses copper pillars and solder caps to form joint and underfill materials to fill the gap. This approach is limited by the size of solder cap and underfill material, which could cause voids between joints. Further shrinking to fine pitch requires copper-to-copper direct bonding (or hybrid bonding), both to reduce package thickness and to provide better electrical performance.

To address issues with TSV stacking and enable 3D-IC packages for future HS/HF applications, DuPont has established a copper-polymer hybrid bonding program aimed at creating this new packaging architecture and reducing memory packaging thickness. The keys to the process are a polymer with dielectric and bonding properties, the right grain structure and high purity for void-free copper-to-copper bonding, and selective simultaneous chemical-mechanical planarization (CMP) of polymers and copper.

Q. Choosing the right polymeric material depends on technical performance          associated with functionality requirements and cost. How does DuPont help      customers choose the right polymeric materials for different steps?

DuPont Electronics & Imaging has many years of experience in developing polymer materials across a broad range of applications, and we have a wide portfolio of polymeric materials. We work closely with our customers, starting from the design stage, and provide materials that solve their technical challenges. These close partnerships with our customers enable both partners to advance our technical leadership in this field.

Besides the technology itself, excellent quality and service are important factors for our customers when selecting suppliers for their materials, and this is a high priority for DuPont Electronics & Imaging. Our products cover many applications, with a strong focus in HS/HF and 5G-related areas. But at the end of the day, we are dedicated to providing our customers with a total solution for their advanced semiconductor packaging and assembly applications, leveraging DuPont’s wide portfolio in solder and copper plating, dielectric, lithography, thermal, and CMP materials and processes.